1. Field of the Invention
The present invention relates generally to VLSI modules and testing thereof, and particularly, to an apparatus and testing methodology for automatically adjusting timing delays of time critical signals present in VLSI modules and printed circuit board units.
2. Discussion of the Prior Art
In the development of VLSI products, careful consideration is paid to external interfaces. These interfaces are typically glueless and are required to support an array of different modules with different timing requirements. The problem lies in the generation of one set of timing delays for external interfaces that handles all timing conditions. The timing delays are for timing critical signals, such as synchronous clocks. One can optimize for nominal timings, worst case, or best case, but, as is often the case, silicon processes inherently drift between nominal and the two extremes. Because of this inherent drift the timing design needs to handle multiple timing cases.
Currently, once the nominal, best and worst case delays are identified, a user typically decides and manually programs the selected delay to use for optimum circuit operation.
It would be highly desirable to provide an automatic process that tests the delays between the VLSI module, printed circuit board (PCB), and external memory module as a unit and, further that automatically adjusts the delay of time critical signals input to time sensitive circuits without operator intervention.